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| MC100LVEP05 2.5V / 3.3V ECL 2-Input Differential AND/NAND Description The MC100LVEP05 is a 2-input differential AND/NAND gate. The MC100LVEP05 is the low voltage version of the MC100EP05 and is functionally equivalent to the EL05 and LVEL05 devices. With AC performance much faster than the LVEL05 device, the MC100LVEP05 is ideal for low voltage applications requiring the fastest AC performance available. The 100 Series contains temperature compensation. Features http://onsemi.com MARKING DIAGRAMS* 8 1 TSSOP-8 DT SUFFIX CASE 948R 8 KU05 ALYWG G * * * * * * * * 220 ps Typical Propagation Delay Input Clock Frequency > 3 GHz 0.2 ps Typical RMS Random Clock Period Jitter LVPECL Mode Operating Range: VCC = 2.375 V to 3.6 V with VEE = 0 V NECL Mode Operating Range: VCC = 0 V with VEE = -2.375 V to -3.6 V Open Input Default State Q Output Will Default LOW with Inputs Open These are Pb-Free Devices* 1 1 4 6N MG G DFN8 MN SUFFIX CASE 506AA K M A L = MC100 = Date Code = Assembly Location = Wafer Lot Y = Year W = Work Week G = Pb-Free Package (Note: Microdot may be in either location) *For additional marking information, refer to Application Note AND8002/D. ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 7 of this data sheet. *For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. (c) Semiconductor Components Industries, LLC, 2007 1 May, 2007 - Rev. 0 Publication Order Number: MC100LVEP05/D MC100LVEP05 Table 1. PIN DESCRIPTION D0 1 8 VCC Q, Q D0 2 7 Q VCC VEE EP D1 3 6 Q Pin D0*, D1*, D0**, D1** Function ECL Data Inputs ECL Data Outputs Positive Supply Negative Supply Exposed pad must be connected to a sufficient thermal conduit. Electrically connect to the most negative supply or leave floating open. * Pins will default LOW when left open. ** Pins will default to VCC/2when left open. D1 4 5 VEE Table 2. TRUTH TABLE D0 D1 L H L H D0 H H L L D1 H L H L Q L L L H Q H H H L Figure 1. 8-Lead Pinout (Top View) and Logic Diagram L L H H Table 3. ATTRIBUTES Characteristics Internal Input Pulldown Resistor Internal Input Pullup Resistor ESD Protection Human Body Model Machine Model Charged Device Model Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) TSSOP-8 DFN8 Flammability Rating Transistor Count Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, see Application Note AND8003/D. Oxygen Index: 28 to 34 Pb Pkg Level 1 Level 1 > 4 kV > 200 V > 2 kV Pb-Free Pkg Level 3 Level 1 Value 75 kW 37.5 kW UL 94 V-0 @ 0.125 in 167 Devices http://onsemi.com 2 MC100LVEP05 Table 4. MAXIMUM RATINGS Symbol VCC VEE VI Iout TA Tstg qJA qJC qJA Tsol Parameter PECL Mode Power Supply NECL Mode Power Supply PECL Mode Input Voltage NECL Mode Input Voltage Output Current Operating Temperature Range Storage Temperature Range Thermal Resistance (Junction-to-Ambient) Thermal Resistance (Junction-to-Case) Thermal Resistance (Junction-to-Ambient) Wave Solder 0 lfpm 500 lfpm Standard Board 0 lfpm 500 lfpm 3 sec @ 260C TSSOP-8 TSSOP-8 TSSOP-8 DFN8 DFN8 Condition 1 VEE = 0 V VCC = 0 V VEE = 0 V VCC = 0 V Continuous Surge VI v VCC VI w VEE Condition 2 Rating 6 -6 6 -6 50 100 -40 to +85 -65 to +150 185 140 41 to 44 129 84 265 Unit V V V V mA mA C C C/W C/W C/W C/W C/W C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. Table 5. 100EP DC CHARACTERISTICS, PECL VCC = 2.5 V, VEE = 0 V (Note 2) -40 C Symbol IEE VOH VOL VIH VIL VIHCMR Characteristic Power Supply Current Output HIGH Voltage (Note 3) Output LOW Voltage (Note 3) Input HIGH Voltage (Single-Ended) Input LOW Voltage (Single-Ended) Input HIGH Voltage Common Mode Range (Differential Configuration) (Notes 4, 5) Input HIGH Current Input LOW Current D D 0.5 -150 Min 15 1355 555 1355 555 1.2 Typ 25 1480 730 Max 32 1605 900 1620 900 2.5 Min 17 1355 555 1355 555 1.2 25C Typ 27 1480 730 Max 36 1605 900 1620 900 2.5 Min 19 1355 555 1355 555 1.2 85C Typ 28 1480 730 Max 38 1605 900 1620 900 2.5 Unit mA mV mV mV mV V IIH IIL 150 0.5 -150 150 0.5 -150 150 mA mA NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 2. Input and output parameters vary 1:1 with VCC. VEE can vary +0.125 V to -1.3 V. 3. All loading with 50 W to VCC - 2.0 V. 4. Single-ended input CLK pin operation is limited to VCC 3.0 V in PECL mode. 5. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. http://onsemi.com 3 MC100LVEP05 Table 6. 100EP DC CHARACTERISTICS, PECL VCC = 3.3 V, VEE = 0 V (Note 6) -40 C Symbol IEE VOH VOL VIH VIL VIHCMR Characteristic Power Supply Current Output HIGH Voltage (Note 7) Output LOW Voltage (Note 7) Input HIGH Voltage (Single-Ended) Input LOW Voltage (Single-Ended) Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 8) Input HIGH Current Input LOW Current D D 0.5 -150 Min 15 2155 1355 2075 1355 1.2 Typ 25 2280 1530 Max 32 2405 1700 2420 1675 3.3 Min 17 2155 1355 2075 1355 1.2 25C Typ 27 2280 1530 Max 36 2405 1700 2420 1675 3.3 Min 19 2155 1355 2075 1355 1.2 85C Typ 28 2280 1530 Max 38 2405 1700 2420 1675 3.3 Unit mA mV mV mV mV V IIH IIL 150 0.5 -150 150 0.5 -150 150 mA mA NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 6. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to -2.2 V. 7. All loading with 50 W to VCC - 2.0 V. 8. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. http://onsemi.com 4 MC100LVEP05 Table 7. 100EP DC CHARACTERISTICS, NECL VCC = 0 V, VEE = -2.375 V to -3.6 V (Note 9) -40 C Symbol IEE VOH VOL VIH VIL VIHCMR Characteristic Power Supply Current Output HIGH Voltage (Note 10) Output LOW Voltage (Note 10) Input HIGH Voltage (Single-Ended) Input LOW Voltage (Single-Ended) Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 11) Input HIGH Current Input LOW Current D D 0.5 -150 Min 15 -1 145 -1945 -1 165 -1945 VEE+1.2 Typ 25 -1020 -1770 Max 32 -895 -1600 -880 -1600 0.0 Min 17 -1 145 -1945 -1 165 -1945 VEE+1.2 25C Typ 27 -1020 -1770 Max 36 -895 -1600 -880 -1600 0.0 Min 19 -1 145 -1945 -1 165 -1945 VEE+1.2 85C Typ 28 -1020 -1770 Max 38 -895 -1600 -880 -1600 0.0 Unit mA mV mV mV mV V IIH IIL 150 0.5 -150 150 0.5 -150 150 mA mA NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 9. Input and output parameters vary 1:1 with VCC. 10. All loading with 50 W to VCC - 2.0 V. 11. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. Table 8. AC CHARACTERISTICS VCC = 0 V; VEE = -2.375 V to -3.6 V or VCC = 2.375 V to 3.6 V; VEE = 0 V (Note 12) -40 C Symbol fmax tPLH, tPHL tJITTER VPP tr tf Characteristic Maximum Frequency (Figure 2) Propagation Delay to Output Differential RMS Random Clock Jitter fin v (Figure 2) Input Voltage Swing (Differential Configuration) Output Rise/Fall Times (20% - 80%) Q 3.0 GHz 150 70 Min 3.0 160 210 0.2 800 120 260 1 1200 170 150 80 Typ Max Min 3.0 170 220 0.2 800 130 270 1 1200 180 150 100 25C Typ Max Min 3.0 210 260 0.2 800 150 320 1.5 1200 200 85C Typ Max Unit GHz ps ps mV ps NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 12. Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 W to VCC - 2.0 V. http://onsemi.com 5 MC100LVEP05 850 VOUTamplitude (mVpp) 750 3.3 V 650 550 450 350 250 1.0 10 9 8 7 6 5 4 3 2 1 0 1.5 2.0 2.5 FREQUENCY (GHz) 3.0 Figure 2. Fmax @ 255C Q Driver Device Q Zo = 50 W D Receiver Device Zo = 50 W 50 W 50 W D VTT VTT = VCC - 2.0 V Figure 3. Typical Termination for Output Driver and Device Evaluation (See Application Note AND8020/D - Termination of ECL Logic Devices.) http://onsemi.com 6 MC100LVEP05 ORDERING INFORMATION Device MC100LVEP05DTG MC100LVEP05DTR2G MC100LVEP05MNTXG Package TSSOP-8 (Pb-Free) TSSOP-8 (Pb-Free) DFN8 (Pb-Free) Shipping 100 Units / Rail 2500 / Tape & Reel 1000 / Tape & Reel For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Resource Reference of Application Notes AN1405/D AN1406/D AN1503/D AN1504/D AN1568/D AN1672/D AND8001/D AND8002/D AND8020/D AND8066/D AND8090/D ECL Clock Distribution Techniques Designing with PECL (ECL at +5.0 V) ECLinPSt I/O SPiCE Modeling Kit Metastability and the ECLinPS Family Interfacing Between LVDS and ECL The ECL Translator Guide Odd Number Counters Design Marking and Date Codes Termination of ECL Logic Devices Interfacing with ECLinPS AC Characteristics of ECL Devices http://onsemi.com 7 MC100LVEP05 PACKAGE DIMENSIONS TSSOP-8 DT SUFFIX PLASTIC TSSOP PACKAGE CASE 948R-02 ISSUE A 8x K REF 0.10 (0.004) M 0.15 (0.006) T U S 2X TU S V S L/2 8 5 L 1 PIN 1 IDENT 4 B -U- 0.25 (0.010) M 0.15 (0.006) T U S A -V- F DETAIL E NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 6. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. MILLIMETERS MIN MAX 2.90 3.10 2.90 3.10 0.80 1.10 0.05 0.15 0.40 0.70 0.65 BSC 0.25 0.40 4.90 BSC 0_ 6_ INCHES MIN MAX 0.114 0.122 0.114 0.122 0.031 0.043 0.002 0.006 0.016 0.028 0.026 BSC 0.010 0.016 0.193 BSC 0_ 6_ C 0.10 (0.004) -TSEATING PLANE D -WG DETAIL E DIM A B C D F G K L M http://onsemi.com 8 MC100LVEP05 PACKAGE DIMENSIONS DFN8 CASE 506AA-01 ISSUE D D A B PIN ONE REFERENCE E NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994 . 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.25 AND 0.30 MM FROM TERMINAL. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. MILLIMETERS MIN MAX 0.80 1.00 0.00 0.05 0.20 REF 0.20 0.30 2.00 BSC 1.10 1.30 2.00 BSC 0.70 0.90 0.50 BSC 0.20 --0.25 0.35 2X 0.10 C 2X 0.10 C 0.10 C 8X 0.08 C SEATING PLANE A1 8X K ECLinPS is a trademark of Semiconductor Components Industries, LLC (SCILLC). ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800-282-9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81-3-5773-3850 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative CCCC CCCC CCCC e/2 1 TOP VIEW A DIM A A1 A3 b D D2 E E2 e K L SIDE VIEW (A3) C D2 e 4 L E2 8 5 8X b 0.10 C A B 0.05 C NOTE 3 BOTTOM VIEW http://onsemi.com 9 MC100LVEP05/D |
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